| Issue Date | Title | Author(s) |
| 2011 | Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tiedindependent gate and symmetricasymmetric options | Vaddi R.; Agarwal R.P.; Dasgupta, Sudeb |
| 2010 | Analytical potential distribution model for underlap double gate MOSFETs with 3T-4T and symmetric-asymmetric options for subthreshold operation: A conformal mapping approach | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2012 | Compact modeling of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operation | Vaddi R.; Agarwal R.P.; Dasgupta, Sudeb |
| 2011 | Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID): Device and circuit co-design | Vaddi R.; Agarwal R.P.; Dasgupta, Sudeb; Kim T.T. |
| 2010 | Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2009 | Device and circuit design challenges in the digital subthreshold region for ultralow-power applications | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2011 | Effect of gate - S/D underlap, asymmetric and independent gate features in the minimization of short channel effects in nanoscale DGMOSFET | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2012 | Enhanced bias-flip rectifier with ultra-low power control for piezo electric energy harvester in the microwatt application scenario | Vaddi R.; Dasgupta, Sudeb |
| 2021 | Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap | Japa A.; Majumder M.K.; Sahoo S.K.; Vaddi R.; Kumar Kaushik, Brajesh |
| 2009 | Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logic | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2011 | Optimization of vertical silicon nanowire based solar cell using 3D TCAD simulation | Kumar J.; Manhas, Sanjeev Kumar; Singh, Dharmendra; Vaddi R. |
| 2010 | Robust and ultra low power subthreshold logic circuits with symmetric, asymmetrie, 3T, 4T DGFinFETs | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2010 | Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2009 | SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2011 | Two dimensional analytical subthreshold current model of a generic double gate MOSFET with gate underlap | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
| 2011 | Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features | Vaddi R.; Dasgupta, Sudeb; Agarwal R.P. |
