| Issue Date | Title | Author(s) |
| 2008 | A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2009 | Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2007 | Analytical modeling of threshold voltage for nanoscale Symmetric Double Gate (SDG) MOSFET with ultra thin body (UTB) | Vishvakarma S.K.; Raj B.; Singh R.; Panda C.R.; Saxena A.K.; Dasgupta, Sudeb |
| 2020 | Comparative Analysis of Spintronic Memories for Low Power on-chip Caches | Singh I.; Raj B.; Khosla M.; Kumar Kaushik, Brajesh |
| 2008 | Evaluation of threshold voltage for 30 nm symmetric double gate (SDG) MOSFET and it's variation with process parameters | Vishvakarma S.K.; Raj B.; Saxena A.K.; Singh R.; Panda C.R.; Dasgupta, Sudeb |
| 2007 | Modeling of the inversion charge density in the nanoscale symmetric double gate MOSFET: An analytical approach | Vishvakarma S.K.; Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2011 | Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2011 | Process variation tolerant FinFET based robust low power SRAM cell design at 32 nm technology | Raj B.; Mitra J.; Bihani D.K.; Rangharajan V.; Saxena A.K.; Dasgupta, Sudeb |
| 2010 | Quantum inversion charge and drain current analysis for double gate FinFET device: Analytical modeling and TCAD simulation approach | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2012 | Quantum mechanical analytical drain current modeling and simulation for double gate FinFET device using quasi Fermi potential approach | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2013 | Quantum mechanical analytical modeling of nanoscale DG FinFET: Evaluation of potential, threshold voltage and source/drain resistance | Raj B.; Saxena A.K.; Dasgupta, Sudeb |
| 2007 | Two dimensional analytical potential modeling of nanoscale Symmetric Double Gate (SDG) MOSFET with ultra thin body (UTB) | Vishvakarma S.K.; Agrawal V.; Raj B.; Dasgupta, Sudeb; Saxena A.K. |
