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Browsing by Author Pal P.K.

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Showing results 1 to 14 of 14
Issue DateTitleAuthor(s)
2015A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectivesPal P.K.; Kaushik B.K.; Anand B.; Dasgupta S.
2016A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metricsPal P.K.; Kaushik B.K.; Dasgupta S.
2015Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability AnalysisPal P.K.; Kaushik B.K.; Dasgupta S.
2014Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETsPal P.K.; Kaushik B.K.; Dasgupta S.
2015Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFETPal P.K.; Nehra D.; Kaushik B.K.; Dasgupta S.
2014High permittivity spacer effects on junctionless FinFET based circuit/SRAM applicationsNehra D.; Pal P.K.; Kaushik B.K.; Dasgupta S.
2013High-performance and robust SRAM cell based on asymmetric dual-k spacer FinfetsPal P.K.; Kaushik B.K.; Dasgupta S.
2015Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOSMahawar S.; Verma S.; Pal P.K.; Kaushik B.K.
2014Investigation of symmetric dual-k spacer trigate FinFETs from delay perspectivePal P.K.; Kaushik B.K.; Dasgupta S.
2014Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETsPal P.K.; Kaushik B.K.; Dasgupta S.
2013Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k SpacersPal P.K.; Kaushik B.K.; Dasgupta S.
2012Performance analysis of dual-k spacer at source side for underlap FinFETsPal P.K.; Singh P.; Kaushik B.K.; Anand B.; Dasgupta S.
2016Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-Spacer NMOSVerma S.; Pal P.K.; Mahawar S.; Kaushik B.K.
2015Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-designPal P.K.; Verma S.; Kaushik B.K.; Dasgupta S.