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Browsing by Author Manhas S.K.

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Issue DateTitleAuthor(s)
2016A compact ridge cavity resonator for concurrent dual-band applicationsSnehalatha L.; Pathak N.P.; Manhas S.K.
2014A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriersShankar R.; Kaushal G.; Maheshwaram S.; Dasgupta S.; Manhas S.K.
2010A high performance vertical Si nanowire CMOS for ultra high density circuitsMaheshwaram S.; Kaushal G.; Manhas S.K.
2017A reconfigurable dual-beam planar antenna with beam switching capabilityLalithamma S.; Pathak N.P.; Manhas S.K.
2017A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationPrakash O.; Maheshwaram S.; Sharma M.; Bulusu A.; Saxena A.K.; Manhas S.K.
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand B.
2019Altering the Schottky Barrier Height and Conductance by Using Metal Nanoparticles in Carbon Nanotubes-Based DevicesKumar N.; Navani N.K.; Manhas S.K.
2019Altering the Schottky Barrier Height and Conductance by Using Metal Nanoparticles in Carbon Nanotubes-Based DevicesKumar N.; Navani N.K.; Manhas S.K.
2015An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applicationsJoshi A.; Manhas S.K.; Sharma S.K.; Dasgupta S.
2012An accurate current source model for CMOS based combinational logic cellKaur B.; Vundavalli S.; Manhas S.K.; Dasgupta S.; Anand B.
2013An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesKaur B.; Miryala S.; Manhas S.K.; Anand B.
2012Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnectsMajumder M.K.; Pandya N.D.; Kaushik B.K.; Manhas S.K.
2012Analysis of crosstalk delay and power dissipation in mixed CNT bundle interconnectsMajumder M.K.; Kaushik B.K.; Manhas S.K.; Kumar J.
2014Analysis of crosstalk delay using mixed CNT bundle based through silicon viasMajumder M.K.; Kumari A.; Kaushik B.K.; Manhas S.K.
2014Analysis of delay and dynamic crosstalk in bundled carbon nanotube interconnectsMajumder M.K.; Kaushik B.K.; Manhas S.K.
2012Analysis of mixed CNT bundle interconnects: Impact on delay and power dissipationMajumder M.K.; Kaushik B.K.; Manhas S.K.
2012Analysis of MWCNT and bundled SWCNT interconnects: Impact on crosstalk and areaMajumder M.K.; Pandya N.D.; Kaushik B.K.; Manhas S.K.
2016Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and SignificancePandey A.; Kumar H.; Manhas S.K.; Dasgupta S.; Anand B.
2011Barrier layer thickness analysis for reliable copper plug process in CMOS technologyManhas S.K.; Singh N.; Lo G.Q.
2016Compact model for vertical silicon nanowire based device simulation and circuit designSharma M.; Maheshwaram S.; Prakash O.; Bulusu A.; Saxena A.K.; Manhas S.K.