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Browsing by Author Manhas S.

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Showing results 1 to 5 of 5
Issue DateTitleAuthor(s)
2019Adiabatic logic based full adder design with leakage reduction mechanismsKumar D.; Kumar M.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2019Adiabatic logic based full adder design with leakage reduction mechanismsKumar, Dinesh Senthil; Kumar M.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2019An improved design technique of digital finite impulse response filter for notch filteringKumar A.; Baderia K.; Singh, Girish Kumar; Lee S.; Lee H.-N.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2011Efficient nanoscale VLSI standard cell library characterization using a novel delay modelMiryala S.; Kaur B.; Anand, Bulusu; Manhas S.
2017Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performanceMaheshwaram S.; Prakash O.; Sharma M.; Anand, Bulusu; Manhas S.; Kaushik B.K.; Dasgupta S.; Singh V.