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Browsing by Author Maheshwaram S.

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Issue DateTitleAuthor(s)
2014A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriersShankar R.; Kaushal G.; Maheshwaram S.; Dasgupta S.; Manhas S.K.
2010A high performance vertical Si nanowire CMOS for ultra high density circuitsMaheshwaram S.; Kaushal G.; Manhas S.K.
2017A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationPrakash O.; Maheshwaram S.; Sharma M.; Bulusu A.; Saxena A.K.; Manhas S.K.
2016Compact model for vertical silicon nanowire based device simulation and circuit designSharma M.; Maheshwaram S.; Prakash O.; Bulusu A.; Saxena A.K.; Manhas S.K.
2017Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuitsPrakash O.; Beniwal S.; Maheshwaram S.; Bulusu A.; Singh N.; Manhas S.K.
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.; Singh N.
2013Drive matching issues in multi gate CMOS inverterKaushal G.; Maheshwaram S.; Dasgupta S.; Manhas S.K.
2014Effect of load capacitance and input transition time on FinFET inverter capacitancesPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand B.
2013FinFET device capacitances: Impact of input transition time and output loadPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand B.
2013Impact of series resistance on Si nanowire MOSFET performanceKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta S.
2017Lateral silicon nanowire based standard cell design for higher performancePrakash O.; Sharma M.; Bulusu A.; Saxena A.K.; Manhas S.K.; Maheshwaram S.
2015Low power SRAM design for 14 nm GAA Si-nanowire technologyKaushal G.; Jeong H.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Jung S.O.
2014Novel design methodology using LEXT sizing in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Anand B.; Dasgupta S.; Singh N.
2017Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model with ParasiticsPrakash O.; Maheshwaram S.; Sharma M.; Bulusu A.; Manhas S.K.
2012Radiation effects in Si-NW GAA FET and CMOS inverter: A TCAD simulation studyKaushal G.; Rathod S.S.; Maheshwaram S.; Manhas S.K.; Saxena A.K.; Dasgupta S.
2016Reduction of GIDL Using Dual Work-Function Metal Gate in DRAMGautam S.K.; Maheshwaram S.; Manhas S.K.; Kumar A.; Sherman S.; Jo S.H.
2012Tuning source/drain extension profile for current matching in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta S.; Anand B.; Singh N.
2013Vertical nanowire CMOS parasitic modeling and its performance analysisMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.; Singh N.
2017Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performanceMaheshwaram S.; Prakash O.; Sharma M.; Bulusu A.; Manhas S.; Kaushik B.K.; Dasgupta S.; Singh V.
2013Vertical nanowire MOSFET parasitic resistance modelingMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.