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Browsing by Author Kaushal G.

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Showing results 1 to 19 of 19
Issue DateTitleAuthor(s)
2014A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriersShankar R.; Kaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar
2010A high performance vertical Si nanowire CMOS for ultra high density circuitsMaheshwaram S.; Kaushal G.; Manhas, Sanjeev Kumar
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas, Sanjeev Kumar; Kaushal G.; Anand, Bulusu; Singh N.
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand, Bulusu; Singh N.
2013Drive matching issues in multi gate CMOS inverterKaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar
2013Impact of series resistance on Si nanowire MOSFET performanceKaushal G.; Manhas, Sanjeev Kumar; Maheshwaram S.; Dasgupta S.
2013Impact of series resistance on Si nanowire MOSFET performanceKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta, Sudeb
2015Low power SRAM design for 14 nm GAA Si-nanowire technologyKaushal G.; Jeong H.; Maheshwaram S.; Manhas, Sanjeev Kumar; Dasgupta, Sudeb; Jung S.O.
2014Novel design methodology using LEXT sizing in nanowire CMOS logicKaushal G.; Manhas, Sanjeev Kumar; Maheshwaram S.; Anand, Bulusu; Dasgupta, Sudeb; Singh N.
2014Novel design methodology using LEXT sizing in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Anand, Bulusu; Dasgupta S.; Singh N.
2012Radiation effects in Si-NW GAA FET and CMOS inverter: A TCAD simulation studyKaushal G.; Rathod S.S.; Maheshwaram S.; Manhas, Sanjeev Kumar; Saxena A.K.; Dasgupta, Sudeb
2012Tuning source/drain extension profile for current matching in nanowire CMOS logicKaushal G.; Manhas, Sanjeev Kumar; Maheshwaram S.; Dasgupta, Sudeb; Anand, Bulusu; Singh N.
2012Tuning source/drain extension profile for current matching in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta S.; Anand, Bulusu; Singh N.
2013Vertical nanowire CMOS parasitic modeling and its performance analysisMaheshwaram S.; Manhas, Sanjeev Kumar; Kaushal G.; Anand, Bulusu; Singh N.
2013Vertical nanowire CMOS parasitic modeling and its performance analysisMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand, Bulusu; Singh N.
2013Vertical nanowire MOSFET parasitic resistance modelingMaheshwaram S.; Manhas, Sanjeev Kumar; Kaushal G.; Anand, Bulusu
2013Vertical nanowire MOSFET parasitic resistance modelingMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand, Bulusu
2011Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOSMaheshwaram S.; Manhas, Sanjeev Kumar; Kaushal G.; Anand, Bulusu; Singh N.
2011Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOSMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand, Bulusu; Singh N.