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Browsing by Author Karwal V.

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Showing results 1 to 4 of 4
Issue DateTitleAuthor(s)
2019Adiabatic logic based full adder design with leakage reduction mechanismsKumar D.; Kumar M.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2019Adiabatic logic based full adder design with leakage reduction mechanismsKumar, Dinesh Senthil; Kumar M.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2019An improved design technique of digital finite impulse response filter for notch filteringKumar A.; Baderia K.; Singh, Girish Kumar; Lee S.; Lee H.-N.; Manhas S.; Rawat B.S.; Trivedi A.; Karwal V.
2015Timing offset estimation using pilot sequence for UWB-IR receivers in IEEE 802.15.4a channel modelDhiman S.; Tyagi, Anshul; Gupta R.; Karwal V.