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Browsing by Author Dasgupta, Sudeb

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Issue DateTitleAuthor(s)
20176T SRAM cell analysis for DRV and read stabilityRuchi; Dasgupta, Sudeb
2009A 1.2 volt, 90nm, 16-Bit three way segmented digital to analog converter (DAC) for low power applicationsChandrasekhar M.; Dasgupta, Sudeb
2004A compact analytical model for a gaussian doped nanoscale MOSFET and evidence for diminished Short Channel EffectsDatta D.; Dasgupta, Sudeb
2008A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETsRaj B.; Saxena A.K.; Dasgupta, Sudeb
2018A compact physics-based surface potential and drain current model for an S/D Spacer-Based DG-RFETBhattacharjee A.; Dasgupta, Sudeb
2015A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectivesPal P.K.; Kaushik B.K.; Anand B.; Dasgupta, Sudeb
2009A comparative study of 6T, 8T and 9T decanano SRAM cellAthe P.; Dasgupta, Sudeb
2014A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriersShankar R.; Kaushal G.; Maheshwaram S.; Dasgupta, Sudeb; Manhas, Sanjeev Kumar
2016A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metricsPal P.K.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb
2017A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FETBhattacharjee A.; Saikiran M.; Dasgupta, Sudeb
2019A Hybridized Fuzzy-Neural Predictive Intelligent (HFNPI) Modelling Approach-based Underlap FinFET ModelSharma S.M.; Dasgupta, Sudeb; Kartikeyan, Machavaram Venkata
2011A low-noise, process-variation-tolerant double-gate FinFET based sense amplifierRathod S.S.; Saxena A.K.; Dasgupta, Sudeb
2013A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI CircuitsSingh S.; Kumar Kaushik, Brajesh; Dasgupta, Sudeb
2021A Novel High RSNM RHBD 16T SRAM Cell at 180nmPrakash B.S.; Yadav A.; Bulusu A.; Dasgupta, Sudeb
2019A Novel Twofold Tunnel FET with Reduced Miller Capacitance: Proposal and InvestigationBagga N.; Chauhan N.; Gupta D.; Dasgupta, Sudeb
2017A novel VDSAT extraction method for tunnel FETs and its implication on analog designAcharya A.; Dasgupta, Sudeb; Anand, Bulusu
2010A proposed DG-FinFET based SRAM cell design with RadHard capabilitiesRathod S.S.; Saxena A.K.; Dasgupta, Sudeb
2011A proposed output buffer at 90 nm technology with minimum signal switching noise at 83.3MHzBiswas A.K.; Bulusu A.; Dasgupta, Sudeb
2002A pseudo-two-dimensional model of an n-channel MOSFET under the influence of ionizing radiationChauhan R.K.; Dasgupta, Sudeb; Chakrabarti P.
2020A review on the compact modeling of parasitic capacitance: from basic to advanced FETsSharma S.M.; Singh A.; Dasgupta, Sudeb; Kartikeyan, Machavaram Venkata