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Browsing by Author Dasgupta, Avirup

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Showing results 1 to 20 of 49  next >
Issue DateTitleAuthor(s)
2015A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell sizeNatarajan S.; Agostinelli M.; Akbar S.; Bost M.; Bowonder A.; Chikarmane V.; Chouksey S.; Dasgupta, Avirup; Fischer K.; Fu Q.; Ghani T.; Giles M.; Govindaraju S.; Grover R.; Han W.; Hanken D.; Haralson E.; Haran M.; Heckscher M.; Heussner R.; Jain P.; James R.; Jhaveri R.; Jin I.; Kam H.; Karl E.; Kenyon C.; Liu M.; Luo Y.; Mehandru R.; Morarka S.; Neiberg L.; Packan P.; Paliwal A.; Parker C.; Patel P.; Patel R.; Pelto C.; Pipes L.; Plekhanov P.; Prince M.; Rajamani S.; Sandford J.; Sell B.; Sivakumar S.; Smith P.; Song B.; Tone K.; Troeger T.; Wiedemer J.; Yang M.; Zhang K.
2013A surface potential based model for GaN HEMTsAgnihotri S.; Ghosh S.; Dasgupta, Avirup; Chauhan Y.S.; Khandelwal S.
2017Accurate modeling of centroid shift in III-V FETs including non-linear potential profile and wave-function penetrationSingh D.K.; Dasgupta, Avirup; Chauhan Y.S.
2017An Improved Model for Quasi-Ballistic Transport in MOSFETsDasgupta, Avirup; Agarwal A.; Chauhan Y.S.
2019Analysis and Compact Modeling of Insulator-Metal Transition Material-Based PhaseFET Including Hysteresis and Multidomain SwitchingDasgupta, Avirup; Verma A.; Chauhan Y.S.
2020Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FETKao M.-Y.; Pahwa G.; Dasgupta, Avirup; Salahuddin S.; Hu C.
2014Analysis and modeling of quantum capacitance in III-V transistorsDasgupta, Avirup; Yadav C.; Rastogi P.; Agarwal A.; Chauhan Y.S.
2015ASM-HEMT: Compact model for GaN HEMTsDasgupta, Avirup; Ghosh S.; Chauhan Y.S.; Khandelwal S.
2019Atomistic simulation and compact modeling of atomically thin transistorsChauhan Y.S.; Yadav C.; Dasgupta, Avirup; Rastogi P.
2020BSIM compact model of quantum confinement in advanced nanosheet FETsDasgupta, Avirup; Parihar S.S.; Kushwaha P.; Agarwal H.; Kao M.-Y.; Salahuddin S.; Chauhan Y.S.; Hu C.
2015BSIM-CMG: Standard FinFET compact model for advanced circuit designDuarte J.P.; Khandelwal S.; Medury A.; Hu C.; Kushwaha P.; Agarwal H.; Dasgupta, Avirup; Chauhan Y.S.; Dielacher F.; Pribyl W.; Hueber G.
2020BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel InversionAgarwal H.; Kushwaha P.; Dasgupta, Avirup; Y-Kao M.; Morshed T.; Workman G.; Shanbhag K.; Li X.; Vinothkumar V.; Chauhan Y.S.; Salahuddin S.; Hu C.
2016Capacitance modeling in dual field-plate power GaN HEMT for accurate switching behaviorAhsan S.A.; Ghosh S.; Sharma K.; Dasgupta, Avirup; Khandelwal S.; Chauhan Y.S.
2019Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology NodeKushwaha P.; Agarwal H.; Lin Y.-K.; Dasgupta, Avirup; Kao M.-Y.; Lu Y.; Yue Y.; Chen X.; Wang J.; Sy W.; Yang F.; Chidambaram P.R.C.; Salahuddin S.; Hu C.
2016Characterization of RF Noise in UTBB FD-SOI MOSFETKushwaha P.; Dasgupta, Avirup; Sahu Y.; Khandelwal S.; Hu C.; Chauhan Y.S.
2020Compact Model for Geometry Dependent Mobility in Nanosheet FETsDasgupta, Avirup; Parihar S.S.; Agarwal H.; Kushwaha P.; Chauhan Y.S.; Hu C.
2018Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D TransitionDasgupta, Avirup; Rastogi P.; Agarwal A.; Hu C.; Chauhan Y.S.
2017Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias EffectSahu Y.; Kushwaha P.; Dasgupta, Avirup; Hu C.; Chauhan Y.S.
2014Compact modeling of flicker noise in HEMTsDasgupta, Avirup; Khandelwal S.; Chauhan Y.S.
2020Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic TransportGaidhane A.D.; Pahwa G.; Dasgupta, Avirup; Verma A.; Chauhan Y.S.
Showing results 1 to 20 of 49  next >