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Browsing by Author Bulusu A.

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Showing results 1 to 10 of 10
Issue DateTitleAuthor(s)
2017A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulationPrakash O.; Maheshwaram S.; Sharma M.; Bulusu A.; Saxena A.K.; Manhas S.K.
2016Compact model for vertical silicon nanowire based device simulation and circuit designSharma M.; Maheshwaram S.; Prakash O.; Bulusu A.; Saxena A.K.; Manhas S.K.
2017Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuitsPrakash O.; Beniwal S.; Maheshwaram S.; Bulusu A.; Singh N.; Manhas S.K.
2012Crosstalk reduction using novel bus encoders in coupled RLC modeled VLSI interconnectsNagendra Babu G.; Kaushik B.K.; Bulusu A.
2016FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on DelayPandey A.; Kumar H.; Goyal P.; Dasgupta S.; Manhas S.K.; Bulusu A.
2017Lateral silicon nanowire based standard cell design for higher performancePrakash O.; Sharma M.; Bulusu A.; Saxena A.K.; Manhas S.K.; Maheshwaram S.
2012Low complexity encoder for crosstalk reduction in RLC modeled interconnectsNagendra Babu G.; Kaushik B.K.; Bulusu A.; Majumder M.K.
2014Nitrogen-terminated semiconducting zigzag gnr fet with negative differential resistanceKumar A.; Kumar V.; Agarwal S.; Basak A.; Jain N.; Bulusu A.; Manhas S.K.
2017Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model with ParasiticsPrakash O.; Maheshwaram S.; Sharma M.; Bulusu A.; Manhas S.K.
2017Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performanceMaheshwaram S.; Prakash O.; Sharma M.; Bulusu A.; Manhas S.; Kaushik B.K.; Dasgupta S.; Singh V.