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Browsing by Author Anand B.

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Showing results 1 to 19 of 19
Issue DateTitleAuthor(s)
2015A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectivesPal P.K.; Kaushik B.K.; Anand B.; Dasgupta S.
2016A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterizationKaur B.; Sharma A.; Alam N.; Manhas S.K.; Anand B.
2012An accurate current source model for CMOS based combinational logic cellKaur B.; Vundavalli S.; Manhas S.K.; Dasgupta S.; Anand B.
2013An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesKaur B.; Miryala S.; Manhas S.K.; Anand B.
2016Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and SignificancePandey A.; Kumar H.; Manhas S.K.; Dasgupta S.; Anand B.
2012Device circuit co-design issues in vertical nanowire CMOS platformMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.; Singh N.
2012Dynamic crosstalk effect in multi-layer graphene nanoribbon interconnectsReddy K.N.; Majumder M.K.; Kaushik B.K.; Manhas S.K.; Anand B.
2014Effect of load capacitance and input transition time on FinFET inverter capacitancesPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand B.
2014Efficient ECSM characterization considering voltage, temperature, and mechanical stress variabilityKaur B.; Alam N.; Manhas S.K.; Anand B.
2011Efficient nanoscale VLSI standard cell library characterization using a novel delay modelMiryala S.; Kaur B.; Anand B.; Manhas S.
2013FinFET device capacitances: Impact of input transition time and output loadPandey A.; Raycha S.; Maheshwaram S.; Manhas S.K.; Dasgupta S.; Saxena A.K.; Anand B.
2014Novel design methodology using LEXT sizing in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Anand B.; Dasgupta S.; Singh N.
2012Optimized delay and power performances in multilayer graphene nanoribbon interconnectsReddy K.N.; Majumder M.K.; Kaushik B.K.; Anand B.; Das P.K.
2012Performance analysis of dual-k spacer at source side for underlap FinFETsPal P.K.; Singh P.; Kaushik B.K.; Anand B.; Dasgupta S.
2012Tuning source/drain extension profile for current matching in nanowire CMOS logicKaushal G.; Manhas S.K.; Maheshwaram S.; Dasgupta S.; Anand B.; Singh N.
2013Vertical nanowire CMOS parasitic modeling and its performance analysisMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.; Singh N.
2013Vertical nanowire MOSFET parasitic resistance modelingMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.
2014Vertical nanowire transistor-based CMOS: VTC analysisMaheshwaram S.; Manhas S.K.; Anand B.
2011Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOSMaheshwaram S.; Manhas S.K.; Kaushal G.; Anand B.; Singh N.