Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
Author Scopus IDs
Published In
Help
Sign on to:
My Repository
Receive email
updates
Edit Profile
IITR's Institutional Repository
Browsing by Author Anand, Bulusu
Jump to:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
or enter first few letters:
Sort by:
title
issue date
submit date
In order:
Ascending
Descending
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Authors/Record:
All
1
5
10
15
20
25
30
35
40
45
50
Showing results 1 to 20 of 156
next >
Issue Date
Title
Author(s)
2015
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
Pal P.K.
;
Kumar Kaushik, Brajesh
;
Anand, Bulusu
;
Dasgupta S.
2015
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
Pal P.K.
;
Kaushik B.K.
;
Anand, Bulusu
;
Dasgupta S.
2016
A Framework to Simulate Semiconductor Devices Using Parallel Computer Architecture
Kumar G.
;
Singh M.
;
Anand, Bulusu
;
Trivedi G.
;
Ray P.
;
Santra S.B.
2020
A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design
Kumar C.I.
;
Anand, Bulusu
2020
A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design
Kumar C.I.
;
Anand, Bulusu
2019
A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design
Kumar C.I.
;
Anand, Bulusu
2019
A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design
Kumar C.I.
;
Anand, Bulusu
2018
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects
Pandey A.
;
Garg P.
;
Tyagi S.
;
Ranjan R.
;
Anand, Bulusu
2018
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects
Pandey A.
;
Garg P.
;
Tyagi S.
;
Ranjan R.
;
Anand, Bulusu
2019
A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits
Banchhor S.
;
Kumar K.D.
;
Dwivedi A.
;
Anand, Bulusu
2019
A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits
Banchhor S.
;
Kumar K.D.
;
Dwivedi A.
;
Anand, Bulusu
2021
A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors
Banchhor S.
;
Chauhan N.
;
Anand, Bulusu
2021
A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors
Banchhor S.
;
Chauhan N.
;
Anand, Bulusu
2016
A novel energy-efficient self-correcting methodology employing INWE
Kumar C.I.
;
Sharma A.
;
Miryala S.
;
Anand, Bulusu
2021
A Novel High RSNM RHBD 16T SRAM Cell at 180nm
Prakash B.S.
;
Yadav A.
;
Anand, Bulusu
;
Dasgupta S.
2017
A novel VDSAT extraction method for tunnel FETs and its implication on analog design
Acharya A.
;
Dasgupta, Sudeb
;
Anand, Bulusu
2017
A novel VDSAT extraction method for tunnel FETs and its implication on analog design
Acharya A.
;
Dasgupta S.
;
Anand, Bulusu
2016
A parallel device simulator based on finite element method
Kumar G.
;
Singh M.
;
Trivedi G.
;
Anand, Bulusu
;
Tran Q.-N.
;
Deligiannidis L.
;
Arabnia H.R.
2021
A physical insight into variation aware minimum v DDfor deep subthreshold operation of FinFET
Yadav S.
;
Chauhan N.
;
Tyagi S.
;
Sharma A.
;
Banchhor S.
;
Joshi R.
;
Pratap R.
;
Anand, Bulusu
2021
A physical insight into variation aware minimum v DDfor deep subthreshold operation of FinFET
Yadav S.
;
Chauhan N.
;
Tyagi S.
;
Sharma A.
;
Banchhor S.
;
Joshi R.
;
Pratap R.
;
Anand, Bulusu