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Browsing by Author Sarkar S.

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Showing results 47 to 57 of 57 < previous 
Issue DateTitleAuthor(s)
2012Signature of an antiferromagnetic metallic ground state in heavily electron-doped Sr 2FeMoO 6Jana S.; Meneghini C.; Sanyal P.; Sarkar S.; Saha-Dasgupta T.; Karis O.; Ray S.
2002Space-time evolution of ultra-relativistic heavy ion collisions and hadronic spectraPatra, Binoy Krishna; Alam J.-E.; Roy P.; Sarkar S.; Sinha B.
2009Structural identification and cytotoxic activity of a polysaccharide from the fruits of Lagenaria siceraria (Lau)Ghosh, Kaushik; Chandra K.; Ojha A.K.; Sarkar S.; Islam S.S.
2016Structure of Te80 52132: The two-particle and two-hole spectrum of Sn82 50132Biswas S.; Palit R.; Navin A.; Rejmund M.; Bisoi A.; Sarkar M.S.; Sarkar S.; Bhattacharyya S.; Biswas D.C.; Caamaño M.; Carpenter M.P.; Choudhury D.; Clément E.; Danu L.S.; Delaune O.; Farget F.; De France G.; Hota S.S.; Jacquot B.; Lemasson A.; Mukhopadhyay S.; Nanal V.; Pillay R.G.; Saha S.; Sethi J.; Singh P.; Srivastava, Praveen Chandra; Tandel S.K.
2005Terminating load dependent width optimization of global inductive VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2016Thermally aware performance analysis of single-walled carbon nanotube bundle as VLSI interconnectsRai M.K.; Kumar Kaushik, Brajesh; Sarkar S.
2018Toeplitz and asymptotic Toeplitz operators on H2(Dn)Maji, Amit; Sarkar J.; Sarkar S.
2007Voltage scaling - A novel approach for crosstalk reduction in global VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect loadKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2007Waveform analysis and delay prediction in simultaneously switching CMOS gate driven inductively and capacitively coupled on-chip interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2006Width optimization of global inductive VLSI interconnectsKumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.