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Browsing by Author Agarwal R.P.

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Showing results 20 to 33 of 33 < previous

Issue Date	Title	Author(s)
2011	Implementation of adaptive FIR filter for pulse doppler radar	Mandal A.; Kumar Kaushik, Brajesh; Kumar B.; Agarwal R.P.
2010	Implementation of coordinate rotation algorithm for Digital Phase Locked Loop system in in-phase and quadrature channel signal processing	Mandal A.; Kumar Kaushik, Brajesh; Tyagi K.C.; Agarwal R.P.; Kumar A.
2009	Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logic	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011	Repeater insertion in crosstalk-aware inductively and capacitively coupled interconnects	Kumar Kaushik, Brajesh; Agarwal R.P.; Sarkar S.; Joshi R.C.; Chauhan D.S.
2010	Robust and ultra low power subthreshold logic circuits with symmetric, asymmetrie, 3T, 4T DGFinFETs	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2010	Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2009	SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2005	Terminating load dependent width optimization of global inductive VLSI interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2011	Two dimensional analytical subthreshold current model of a generic double gate MOSFET with gate underlap	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011	Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2007	Voltage scaling - A novel approach for crosstalk reduction in global VLSI interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2007	Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2007	Waveform analysis and delay prediction in simultaneously switching CMOS gate driven inductively and capacitively coupled on-chip interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2006	Width optimization of global inductive VLSI interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.

Showing results 20 to 33 of 33 < previous