IITR's Institutional Repository: Browsing Repository

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:

Showing results 10 to 29 of 33 < previous next >

Issue Date	Title	Author(s)
2009	Crosstalk analysis of simultaneously switching interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2011	Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID): Device and circuit co-design	Vaddi R.; Agarwal R.P.; Dasgupta, Sudeb; Kim T.T.
2011	Design and implementation of CORDIC processor for complex DPLL	Mandal A.; Kumar Kaushik, Brajesh; Kumar B.; Agarwal R.P.
2010	Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2009	Device and circuit design challenges in the digital subthreshold region for ultralow-power applications	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011	Duality in nondifferentiable minimax fractional programming with B-(p, r)-invexity	Ahmad I.; Gupta, Shiv Kumar; Kailey N.; Agarwal R.P.
2011	Effect of gate - S/D underlap, asymmetric and independent gate features in the minimization of short channel effects in nanoscale DGMOSFET	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2007	Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.; Joshi R.C.
2015	FDTD technique based crosstalk analysis of bundled SWCNT interconnects	Duksh Y.S.; Kumar Kaushik, Brajesh; Agarwal R.P.
2011	Generalized second-order mixed symmetric duality in nondifferentiable mathematical programming	Ahmad I.; Agarwal R.P.; Gupta, Shiv Kumar; Kailey N.
2011	Implementation of adaptive FIR filter for pulse doppler radar	Mandal A.; Kumar Kaushik, Brajesh; Kumar B.; Agarwal R.P.
2010	Implementation of coordinate rotation algorithm for Digital Phase Locked Loop system in in-phase and quadrature channel signal processing	Mandal A.; Kumar Kaushik, Brajesh; Tyagi K.C.; Agarwal R.P.; Kumar A.
2009	Investigation of robustness and performance comparisons of 3T - 4T DG-FinFETs for ultra low power subthreshold logic	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011	Repeater insertion in crosstalk-aware inductively and capacitively coupled interconnects	Kumar Kaushik, Brajesh; Agarwal R.P.; Sarkar S.; Joshi R.C.; Chauhan D.S.
2010	Robust and ultra low power subthreshold logic circuits with symmetric, asymmetrie, 3T, 4T DGFinFETs	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2010	Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2009	SDG vs ADG with tied and independent gate options in the subthreshold logic for ultra low power applications	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2005	Terminating load dependent width optimization of global inductive VLSI interconnects	Kumar Kaushik, Brajesh; Sarkar S.; Agarwal R.P.
2011	Two dimensional analytical subthreshold current model of a generic double gate MOSFET with gate underlap	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.
2011	Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features	Vaddi R.; Dasgupta, Sudeb; Agarwal R.P.

Showing results 10 to 29 of 33 < previous next >

Browsing by Author Agarwal R.P.